Change Log¶
v0.4 (not yet released)¶
v0.3 (July 12, 2022)¶
- Network interface:
clone #522
- Algorithms:
Logic resynthesis engines for MIGs (mig_resyn #414) and AIGs/XAGs (xag_resyn #425)
AQFP buffer insertion & optimization (buffer_insertion, which replaces aqfp_view) and verification (buffer_verification) #478 #483
Technology mapping and optimized network conversion (map) #484
Fast cut enumeration based on static truth tables (fast_cut_enumeration) #474
Resynthesis of a k-LUT network into a graph (klut_to_graph) #502
Conversion of a cover network into a graph (cover_to_graph) #512
Minimize debugging testcase (testcase_minimizer) #542
- Views:
Add bindings to a standard library (binding_view) #489
v0.2 (February 16, 2021)¶
Framework for performing quality and performance experiments #140
- Algorithms:
CNF generation (generate_cnf) #145
SAT-based LUT mapping (satlut_mapping) #122
Miter generation (miter) #148
Combinational equivalence checking (equivalence_checking) #149
CNF based cut enumeration (cnf_cut) #155
Fast cut enumeration for small networks (fast_small_cut_enumeration, contributed by Sahand Kashani-Akhavan) #161
Shannon decomposition (shannon_decomposition) #183
Cleanup LUT networks (cleanup_luts) #191
Extract linear subcircuits in XAGs (extract_linear_circuit and merge_linear_circuit) #204
Linear resynthesis using Paar algorithm (linear_resynthesis_paar) #211
XAG optimization by computing transitive linear fanin #232
SAT-based satisfiability don’t cares checker (satisfiability_dont_cares_checker) #236
XAG optimization based on satisfiability don’t cares (xag_dont_cares_optimization) #237
XMG optimization based on satisfiability don’t cares (xmg_dont_cares_optimization) #239
Create circuit based on spectral equivalence transformation sequences and NPN transformations (apply_spectral_transformations apply_npn_transformations) #263 #301
Exact linear resynthesis using SAT (exact_linear_resynthesis, exact_linear_synthesis) #265
XAG optimization by linear resynthesis (linear_resynthesis_optimization, exact_linear_resynthesis_optimization) #296
Davio decomposition (positive_davio_decomposition, positive_davio_decomposition) #308
Collapse network into single node per output network #309
Generic balancing algorithm #340
Check functional equivalence (circuit_validator) #346
Restructured resubstitution framework (resubstitution), simulation-guided resubstitution (sim_resub) #373
Functional reduction (functional_reduction) #380
Network fuzz testing (network_fuzz_tester) #408
- Utils
Create circuit from integer index list (encode, decode, insert, to_index_list_string) #385
- Resynthesis functions:
Resynthesis function based on DSD decomposition (dsd_resynthesis) #182
Resynthesis function based on Shannon decomposition (shannon_resynthesis) #185
Resynthesis function based on Davio decomposition (positive_davio_resynthesis, negative_davio_resynthesis) #308
Exact resynthesis function for XMGs using XOR3 and majority gates (exact_xmg_resynthesis) #328
- Generators:
Sideways sum generator (sideways_sum_adder, contributed by Jovan Blanuša) #159
Carry lookahead adder (carry_lookahead_adder_inplace) #171
Improved modular multiplication (based on doubling modular_multiplication_inplace) #174
Modular doubling and halving (modular_doubling_inplace and modular_halving_inplace) #174 #175
Create modulus vector from hex string for modular arithmetic functions (bool_vector_from_hex) #176
Modular addition based on Hiasat and modular subtraction #177
Majority-9 networks (majority5, majority7, majority9_12, majority9_13) #185
Modular multiplication of Montgomery numbers (montgomery_multiplication) #227
Constant modular multiplication (modular_constant_multiplier) #227
Out-of-place modular addition, subtraction, and multiplication (modular_adder, modular_subtractor, modular_multiplication) #234
Create self-dualization of a logic network (self_dualize_aig) #331
Binary decoder (binary_decoder) #342
2^k MUX (binary_mux and binary_mux_klein_paterson) #342
Random logic networks for XAGs (random_logic_generator) #366
- Properties:
Costs based on multiplicative complexity (multiplicative_complexity and multiplicative_complexity_depth) #170
- Utils:
Computing windows and manipulating cuts (create_window_impl, collect_nodes, collect_inputs, collect_outputs, expand0_towards_tfi, expand_towards_tfi, expand_towards_tfo, levelized_expand_towards_tfo) #381
v0.1 (March 31, 2019)¶
- Algorithms:
Cut enumeration (cut_enumeration) #2
LUT mapping (lut_mapping) #7
Akers synthesis (akers_synthesis) #9
Create LUT network from mapped network (collapse_mapped_network) #13
MIG algebraic depth rewriting (mig_algebraic_depth_rewriting) #16 #58
Cleanup dangling nodes (cleanup_dangling) #16
Node resynthesis (node_resynthesis) #17
Reconvergency-driven cut computation (reconv_cut) #24
Simulate networks (simulate) #25
Simulate node values (simulate_nodes) #28
Cut rewriting (cut_rewriting) #31
Refactoring (refactoring) #34
Exact resynthesis for node resynthesis, cut rewriting, and refactoring #46 #71
Compute satisfiability don’t cares (satisfiability_dont_cares) #70
Compute observability don’t cares (observability_dont_cares) #82
Optimum XMG resynthesis for node resynthesis, cut rewriting, and refactoring #86
XMG algebraic depth rewriting (xmg_algebraic_depth_rewriting) #86
Convert gate-based networks to node-based networks (gates_to_nodes) #90
Direct resynthesis of functions into primitives (direct_resynthesis) #90
XAG optimum multiplicative complexity resynthesis (xag_minmc_resynthesis) #100
AIG/XAG resynthesis (xag_npn_resynthesis) #102
DSD decomposition (dsd_decomposition) #137
- Views:
Visit nodes in topological order (topo_view) #3
Disable structural modifications to network (immutable_view) #3
View for mapped networks (mapping_view) #7
View compute depth and node levels (depth_view) #16
Cut view (cut_view) #20
Compute MFFC of a node (mffc_view) #34
Compute window around a node (window_view) #41
- I/O:
Read AIGER files using lorina (aiger_reader) #6
Read BENCH files using lorina (bench_reader) #6
Write networks to BENCH files (write_bench) #10
Read Verilog files using lorina (verilog_reader) #40
Write networks to Verilog files (write_verilog) #65
Read PLA files using lorina (pla_reader) #97
Write networks to DOT files (write_dot) #111
- Generators for arithmetic circuits:
Carry ripple adder (carry_ripple_adder) #5
Carry ripple subtractor (carry_ripple_subtractor) #32
Carry ripple multiplier (carry_ripple_multiplier) #45
Modular adder (modular_adder_inplace) #43
Modular subtractor (modular_subtractor_inplace) #43
Modular multiplication (modular_multiplication_inplace) #48
2k-to-k multiplexer (mux_inplace) #43
Zero padding (zero_extend) #48
Random logic networks for AIGs and MIGs (random_logic_generator) #68
- Utility data structures: truth_table_cache, cut, cut_set, node_map, progress_bar, stopwatch