mockturtle
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Getting started
Compilation requirements
Using mockturtle as a stand-alone tool
Using mockturtle as a library in another project
Building tests
Debugging toolset
Testcase minimizer
Fuzz testing
Debugging utilities
Visualization
Drawing a figure
Printing method
Time machine
Change log
v0.4 (not yet released)
v0.3 (July 12, 2022)
v0.2 (February 16, 2021)
v0.1 (March 31, 2019)
Acknowledgments
Standard library
The
mockturtle
philosophy
Network interface API
Mandatory types and constants
Constructors and copy assignment
Methods
Duplicate network
Primary I/O and constants
Create unary functions
Create binary functions
Create ternary functions
Create nary functions
Create arbitrary functions
Restructuring
Structural properties
Functional properties
Nodes and signals
Node and signal iterators
Simulate values
Custom node values
Visited flags
General methods
Network implementations
Supplementary network types
Block Network
Cover Network
Crossed Network
Buffered Networks
Generic Network
Sequential networks
Storing register information
Sequential interface APIs
Views
topo_view
: Ensure topological order
depth_view
: Compute levels and depth
rank_view
: Order nodes within each level
mapping_view
: Add mapping interface methods
cut_view
: Network view on a single rooted cut
mffc_view
: Network view on a (M)FFC
immutable_view
: Prevent network changes
fanout_view
: Compute fanout
window_view
: Network view on a window
binding_view
: Add bindings from a technology library
cell_view
: Add cell mappings from a technology library
names_view
: Assign names to signals and outputs
choice_view
: Implements choices in networks
dont_touch_view
: Mark nodes as “don’t touch”
cnf_view
: Creates a CNF while creating a network
color_view
: Manages traversal IDs
cost_view
: Manages global cost and maintains context
dont_care_view
: Manages external don’t care information
Network events
Algorithms
Decomposition
DSD decomposition
Shannon and Davio decomposition
Bi-decomposition
Network information extraction
Network simulation
Simulators
Partial simulation
Simulation pattern generation
Parameters and statistics
Algorithm
Don’t cares
Cut enumeration
Parameters
Return value
Algorithm
Pre-defined cut types
Special-purpose implementations
Reconvergence-driven cuts
Extract linear subcircuit
Extract adders
Logic restructuring and optimization
Akers synthesis
Logic resynthesis
Resynthesize linear circuit
AQFP Resynthesis
AQFP Node Resynthesis
AQFP Fanout Resynthesis
Rewrite
Parameters and statistics
Algorithm
Rewriting functions
Cut rewriting
Parameters and statistics
Algorithm
Rewriting functions
XAG algebraic rewriting
Parameters
Algorithm
MIG algebraic rewriting
Parameters
Algorithm
Resubstitution
Parameters and statistics
Structure
Detailed statistics
Various XAG optimization algorithms
Various XMG optimization algorithms
Functional reduction
Parameters and statistics
Algorithm
Refactoring
Parameters and statistics
Algorithm
Rewriting functions
AIG balancing
Parameters
Algorithm
XAG balancing
Parameters
Algorithm
Balancing
Parameters and Statistics
Algorithm
Rebalancing engines
Cost-generic resubstitution algorithm
Customized cost function
Algorithm
Network transformation and mapping
Extended technology mapping
Technology mapping and network conversion
LUT mapping 1
Dynamic-programming based heuristic
LUT mapping 2
Dynamic-programming based heuristic
SAT-based mapping
Collapse mapped network
Node resynthesis
Parameters and statistics
Algorithm
Resynthesis functions
k-LUT to graph conversion
Algorithm
COVER to graph conversion
Gate-based network to node-based network
Algorithm
Cleanup networks
Transformations based on equivalence classes
Algorithms
AQFP buffer insertion and verification
Technology assumptions
Buffer insertion algorithms
Parameters
Buffered network data structure
Verification of buffered networks
Retiming
Validation and verification
Functional equivalence of circuit nodes
CNF generation
Miter generation
Equivalence checking
Parameters and statistics
Algorithm
Input/Output
Lorina readers
Write into file formats
Write into AIGER files
Write into BENCH files
Write into BLIF files
Write into structural Verilog files
Write into DIMACS files (CNF)
Write into DOT files (Graphviz)
Write simulation patterns into file
Write library into GENLIB file
Generators
Arithmetic networks
Addition and Subtraction
Control logic
Majority-n networks
Modular arithmetic networks
Addition and Subtraction
Multiplication
Utility functions
Properties
Properties
MIG-based costs
Multiplicative complexity costs
Factored form literals costs
Utilities
Utility data structures
Truth table cache
Node map
Tech library
Exact library
Supergates utils
Struct library
Cuts
Cut sets
Index list
Stopwatch
Progress bar
Utility functions
Manipulate windows with network data types
Restore network and PI/PO names
mockturtle
Decomposition
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Decomposition
DSD decomposition
Shannon and Davio decomposition
Bi-decomposition
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